Amdrel a low-energy FPGA architecture and supporting CAD tool design flow

Abstract

FPGAs have recently benefited from technology process advances to become significant alternatives to Application Specific Integrated Circuits (ASICs). An important feature that has made FPGAs, particularly attractive is a logic mapping and implementation flow similar to the ASIC design flow (from VHDL or Verilog down to the configuration bitstream) provided by the industrial sector [1, 2]. However, in order to implement real-life applications on an FPGA platform, embedded or discrete, increasingly performance and power-efficient FPGA architectures are required. Furthermore, efficient architectures cannot be used effectively without a complete set of tools for implementing logic while utilizing the advantages and features of the target device. Consequently, research has lately focused on the development of FPGA architectures [3, 4, 5, 6, 7, 8] as mentioned in Chapter I. Many solid efforts for the development of a complete tool design flow from the academic sector have also taken place ([6, 9, 10]). The above design groups have focused on the development of tools that can target a variety of FPGA architectures, while keeping the tools open-source. Despite the above efforts, there is a gap in the complete design flow (from VHDL to configuration bit-stream) provided by existing academic tools. This is due to the lack of an open-source synthesizer and a FPGA configuration bit-stream generation tool. Therefore, there is no existing complete academic system capable of implementing, in a FPGA, logic specified in a hardware description language. Just an assortment of various fine-grain architectures and tools that cannot be easily integrated into a complete system. In this chapter, such a complete system is presented. The hardware design of an efficient FPGA architecture is presented in detail. An exploration in terms of power, delay and area at both Configurable Logic Block (CLB) design and interconnection architecture has been applied in order to make appropriate architecture decisions. Particularly, Basic Logic Element (BLE) using gated clock approach is investigated, at CLB level, while at the interconnect network level, new research results about the type and sizing of routing switches are presented in 0.18m process. This investigation is mostly focused on minimizing power dissipation, since this was our primary target in this FPGA implementation, without significantly degrading delay and area. Additionally, a complete toolset for mapping logic on the FPGA mentioned above is presented, starting from a VHDL circuit description down to the FPGA configuration bitstream. The framework is composed of i) non-modified academic tools, ii) modified academic tools and iii) new tools. The developed tool framework supports a variety of FPGA architectures. The FPGA architecture and tools were developed as part of the AMDREL project [11] and the tools can be run on-line at the AMDREL website. The rest of the chapter is organized as follows: Section 3.2 describes the FPGA hardware platform in detail, while Sect. 3.3 is a brief presentation of the tools. Sect. 3.4 provides a number of quantitative and qualitative comparisons with existing academic and commercial approaches in order to evaluate the entire system of tools and platform. Conclusions are further discussed in Sect. 3.5. . © 2008 Springer.