SAD-Based Stereo Matching Using FPGAs

Abstract

This paper presents a survey of the principal architectures and blocks building up a flash memory, describing how these blocks are designed and how their design has changed over the years to satisfy the new specification requests. For example, the continuous supply voltage reduction aimed at portable electronic solutions has forced designers to find innovative design solutions. An overview of the test modes developed for the flash device not only to debug the chip but also to try to improve reliability is given. Ad hoc test modes are useful to deeply increase the analysis capability. Finally, the test methodology for flash memories, a challenge between the test time reduction and better test coverage, is presented.