3D VG-type NAND flash memories

Abstract

The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack. The most popular cells stacks are Vertical-Channel (VC) and Vertical-Gate (VG). In VC gate-all-around type, the channel is realized by etching a hole through the layers stack in one single step, and then forming the transistor structure with deposition of its ONO charge trapping layers, tunnel oxide and the polysilicon channel fill in the middle. The cell gates are constituted by the polysilicon horizontal layer surrounding the vertical channel forming a Gate-All-Around (GAA) structure. The string current flows in the cells in the vertical direction. In the VG-type the vertical etching is necessary to separate the strings in one direction and to separate the wordlines in the other direction. The current flows in horizontal direction and each layer must be connected to the top metal bitlines and source lines by a proper connecting structure. This chapter digs into the details of Vertical-Gate architectures.