Network-on-Chip Architectures

Abstract

The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Computer architects are actively pursuing multi-core designs with billions of transistors on a single die. Integration at these levels has highlighted the criticality of the on-chip interconnects; global interconnect delays are dominating gate delays and affecting overall system performance. Packet- based Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. NoCs are steadily becoming the de facto intercon- nect solution in complex Systems-on-Chip (SoC), because of their scalability and optimized electrical properties. However, current research also indicates that the chip area and power budgets are increasingly being dominated by the interconnection network. To combat this escalating trend, attention should be paid to the optimization of the interconnect architecture. Unlike traditional multi-computer macro-networks, on-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Scarcity in the area and power budgets devoted to the interconnection fabric necessitates a re-interpretation of the networking paradigm. Furthermore, despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. These conflicting requirements transform the NoC design process into a grand challenge for the system designer. The work presented in this volume aims to address these issues through a comprehensive and holistic exploration of the design space. To truly appreciate the nuances underlying the NoC realm, the design aspects of the on-chip network are viewed through a penta-faceted prism encom- passing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research described in this volume explores the field by employing a two- pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads, along with the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design and integration of NoCs in modern multi-core architectures. Based on this premise of two complementary core themes, the volume is divided into two corresponding parts; the first part delves into the world of MICRO-architectural exploration of the NoC paradigm, while the second part shifts the focus to a MACRO-architectural abstraction level. Ultimately, both parts work in unison in attacking several pressing issues concern- ing on-chip interconnects in the new multi/many-core reality.