A study on non-volatile 3D stacked memory for big data applications

Abstract

Recently, big data processing has been an increasingly important field of computer applications, which has attracted a lot of attention from academia and industry. However, it worsens the memory wall problem for processor design, which means a large performance gap between processor computation and memory access. The stacked memory structure has the potential benefits for future processor design such as low latency, large capacity, and high bandwidth. Since these benefits can effectively relieve the problem of memory wall, stacked memory structure has been a promising architecture technique. Such memory structure began to use non-volatile memory (NVM) to provide a faster and larger memory, but its memory access behaviours for big data application have not been fully studied. In order to understand its memory performance better, this paper analyses the NVM 3D stacked structure using simulation method. Since flash memory is the maturest NVM media, this paper uses flash memory as the NVM part in the stacked structure to study, which results in a processor architecture with tightly connected CPU, DRAM and flash layers. In our experiment, channel number, capacity, page size and latency of read and write are test variables. Through observing the evaluation results of eight programs from big data program set, we conclude that the bandwidth and capacity have a significant effect for big data applications, and as bandwidth and capacity increasing, the Read/Write latency of flash and page size show less affection. We also point out some problems about data consistency, channel selection, read and write strategy and data granularity selection. These analysis results are useful for further study and optimization on NVM 3D stacked structure.