Optimum gate ordering of CMOS logic gates using Euler path approach: Some insights and explanations

Abstract

The paper addresses some insights into the Euler path approach to find out the optimum gate ordering of CMOS logic gates. Minimization of circuit layout area is one of the fundamental considerations in circuit layout synthesis. Euler path approach suggests that finding a common Euler path in both the NMOS and PMOS minimizes the logic gate layout area. In this article, the minimization of layout area has been placed as equivalent to minimization of the total number of odd vertices in NMOS and PMOS networks. It has been logically proved that a MOS network will always have an even number of odd vertices. Moreover, it intuitively explains how to organize the sequence of a NMOS network when deriving the corresponding PMOS network from it, so that the number of odd vertices is minimized. The algorithm to determine the total number of Euler paths is also presented in this article.