Aggressive memory-aware compilation

Abstract

Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this bottleneck. However, such features cannot be efficiently exploited in processor- based embedded systems without memory-aware compiler support. We describe a memory- aware compiler approach that exploits such efficient memory access modes by extracting accurate timing information, allowing the compiler’s scheduler to perform global code reordering to better hide the latency of memory operations. Moreover, we present a compiler technique which in the presence of caches actively manages cache misses, and performs global miss traffic optimizations, to better hide the latency of the memory operations. Our memory-aware compiler scheduled several benchmarks on the TI C6201 processor architecture interfaced with a 2-bank synchronous DRAM and generated average improvements of 24% in the presence of efficient access modes, and 61.6% improvement in the presence of caches, over the best possible schedule using a traditional (memory-transparent) optimizing compiler, demonstrating the utility of our memory-aware compilation approach.