For huge systems like video processing, FPGA prototyping plays an important role before taping out. In this paper, a verification system for H.264/AVC encoders with FPGA prototyping is proposed and implemented. An H.264 encoder with baseline profile of Level 3.2 was carried out with a clock frequency of 200MHz on a Xilinx Virtex-6 FPGA connected with DDR3 memory, which could satisfy real-time encoding for HDTV applications (720P@60fps) with a PSNR around 34 db. The encoder was finally implemented with SMIC 65nm CMOS technology for silicon verification. © 2012 Springer-Verlag GmbH.
CITATION STYLE
Wang, T., Chen, C. K., Yang, Q. H., & Wang, X. A. (2012). FPGA implementation and verification system of H.264/AVC encoder for HDTV applications. In Advances in Intelligent and Soft Computing (Vol. 169 AISC, pp. 345–352). https://doi.org/10.1007/978-3-642-30223-7_54
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