Design, Implementation and Performance Analysis of Shift Register Using Reversible Sayem Gate

Abstract

Reversible logic design in present scenario has gained importance because it releases minimum heat generation in the design circuit which prolongs the lifetime of the circuits. However, in irreversible design, they dissipated more heat due to a large number of internal switching. This paper is mainly focused on the design of the sequential circuits like shift register using reversible gates which is reducing the number of gate counts, garbage outputs and number of constant inputs. The proposed design of shift register is well designed using D-flip flops made by the reversible Sayem gate which will give the low output power and delay of the circuit design and compare the result of conventional master–slave D-flip flop with reversible D-flip flop. The output power and delay of the proposed reversible shift register is proved better in terms of power dissipation and delay by 33.99% and 24.53% respectively. The output of shift register obtained using Cadence Virtuoso tool with 180 nm technology is verified.