Evaluating the metro-on-chip methodology to improve the congestion and routability

Abstract

Recently, metro-on-chip technique has been presented to improve the congestion of design by serializing parallel wires via delay insensitive asynchronous serial transceivers. In this paper, metro-on-chip technique is improved in terms of routability and computation time and also its impact on routability is examined. Finally, it is evaluated in 130nm technology. Experimental results show that for attempted benchmarks, congestion and routability are improved by 15.54% and 21.57% on average, respectively. Total wire length is reduced up to 6.3% with a slightly increasing in power consumption (0.12% on average). © 2008 Springer-Verlag.