Fast statistical modelling of temperature variation on 28 nm FDSOI technology

Abstract

It is well known that the 28 nm fully depleted Silicon-On Insulator (FDSOI) node has a temperature effect due to the inherent pyroelectric and piezoelectric properties. In this paper, we introduce a spatial interpolation Lookup table (LUT) model considering temperature dependence of nanometer CMOS transistors. The novel methodology is used to build the bias current and capacitance LUTs for MOS transistor circuits under extensive variety of temperature values, evaluated under transient analysis. This innovative LUTs model significantly reduce the simulation runtime with sufficient accuracy using adaptive multivariate precomputed Barycentric relational interpolation for the appraisal temperature effects of 28 nm FDSOI node. A transient analysis benchmark is employed in order to verify and validate the proposed models according to the well-known simulation models (i.e. the 28 nm FDSOI model and traditional spatial Lagrange model). The proposed model can significantly reduce the size of lookup table, thereby reducing the computational cost. Furthermore, the model outperform the 28 nm FDSOI compact physical model and the traditional spatial Lagrange model due to the reduced simulation runtime by up to eight orders of magnitude considering the temperature effect in 28 nm FDSOI innovation. Moreover, the proposed novel LUT based approaches are able to attain high precision with much reduced computational cost.