Design and Implementation of Rough Set Algorithms on FPGA: A Survey

Abstract

Rough set theory is a mathematical approach to process and interpret in¬complete information system. Several researchers have dealt with the problem of finding reduct from the set of attributes, cores, and rules from databases using different soft¬ware deployed on multiprocessor system. Recently researchers have started using Field Programmable Gate Array (FPGA) implementation as an alternate option. Software approach is versatile but slow as compared to hardware implementation. The goal of this work is to design an exemplary rough set co-processor based on rough set theory and map it on FPGA. This paper gives an insight of a rough set co-processor’s modules. The theory of dealing with large databases is studied. With the usage of dual port RAM and pipelining in design, a considerable time is saved thus making it suitable for real time applications. The application for rough set co-processor is explained with the case study of a typical fault dictionary of a Very Large Scale Integrated (VLSI) chip. It can be used as a Built-in-Self-Test controller for testing VLSI chip. Simulation results show that proposed hardware is significantly faster than algorithms running on general-purpose processor. The rough set co-processor can also be used as hardware classifier unit in per¬sonal computer.