Advanced physical design in nanoscale analog CMOS

Abstract

As the EDA industry strives to keep pace with advancements in process technology, CMOS IC verification tools are identifying a wider range of circuit and physical design deficiencies. While the EDA tools have shown considerable progress, problems found in post-layout verification can result in significant additional redesign and re-layout time. Circuit and layout redesign effort wastes the semiconductor industries most valuable commodity, time to market. One objective of this paper is to identify many factors adversely affecting successful nanoscale analog physical design. However, the primary objective is to propose methods for mitigating or overcoming physical design problems, so that the future of deep-nanoscale analog CMOS looks a bit brighter. One key to the basic approach is to propose certain restrictions on device design at the initial circuit design stage and another is to achieve increased regularity in physical design at circuit layout. © 2011 Springer Science+Business Media B.V.