High throughput and area efficient FPGA implementation of AES algorithm

ISSN: 22498958
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Now a days, digital data is very easy to process but it permits unauthorized consumers to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the best and commonly used symmetric key cryptographic algorithm. Main aim of this article is to implement fast and safe AES algorithm on reconfigurable platform. AES algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.




Mane, P. B., & Mulani, A. O. (2019). High throughput and area efficient FPGA implementation of AES algorithm. International Journal of Engineering and Advanced Technology, 8(4), 519–523.

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