Design and FPGA Implementation of Vedic Notch and Peak Filters

Abstract

These days, in digital filters, high speed and low complexity are the key requirements. In this paper, notch and peak filters are proposed to design using high speed Vedic multipliers. Vedic multipliers are designed using high speed carry save adders and carry select adders. A design example is included to analyze the effectiveness of the proposed filters using direct form II structure and has been tested and verified on Xilinx ZYNC field programmable gate array (FPGA) device. The performance of the proposed Vedic notch and peak filters (VNPF) is compared in terms of utilized hardware and power dissipation. It is shown that the proposed VNPF is consuming less power and occupying small hardware compared to the conventional notch and peak filters.