Fault-tolerant optimization for application-specific network-on-chip architecture

Abstract

Advanced integration technologies enable the construction of Network-on-Chip (NoC) from two dimensions to three dimensions. Studies have shown that 3D NoCs can improve average communication performance because of the possibility of using the additional dimension to shorten communication distance. This paper presents a defect tolerance technique for recovering permanent routers failure through an efficient and effective use of redundancy. This technique is ideally suited for three and even two dimensional network-on-chip (NoC). This fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented. Simulation results demonstrate significant reliability and yield improvement. Although the hardware overhead of the 3D (2D)-proposed methodology compare with traditional mesh is approximately 15 % (12 %), it improves the average response time of system up to 31 % (23 %). © 2014 Springer Science+Business Media Dordrecht.