Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs by using a heterogeneous interconnect. Our proposal consists of Reply Partitioning, a technique that classifies all coherence messages into critical and short, and non-critical and long messages; and the use of a heterogeneous interconnection network comprised of low-latency wires for critical messages and low-energy wires for non-critical ones. Through detailed simulations of 8-and 16-core CMPs, we show that our proposal obtains average improvements of 8% in execution time and 65% in the Energy-Delay2 Product metric of the interconnect over previous works. © Springer-Verlag Berlin Heidelberg 2007.
CITATION STYLE
Flores, A., Aragón, J. L., & Acacio, M. E. (2007). Efficient message management in tiled CMP architectures using a heterogeneous interconnection network. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4873 LNCS, pp. 133–146). Springer Verlag. https://doi.org/10.1007/978-3-540-77220-0_16
Mendeley helps you to discover research relevant for your work.