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UVM (Universal Verification Methodology)

  • Mehta A
Springer International Publishing, (2018), 17-64
DOI: 10.1007/978-3-319-59418-7_4
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Abstract

This chapter will describe in detail the architecture of UVM, UVM hierarchy, and discuss each hierarchical component (testbench, test, environment, agent, scoreboard, driver, monitor, sequencer, etc.) in detail. We will also go through two complete examples to solidify the concepts.

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APA

Mehta, A. B. (2018). UVM (Universal Verification Methodology). In ASIC/SoC Functional Design Verification (pp. 17–64). Springer International Publishing. https://doi.org/10.1007/978-3-319-59418-7_4

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