Advances in Parallel Transistor-Level Circuit Simulation

Abstract

Parallel transistor-level circuit simulation has the potential to signifi-cantly impact the need for reliably determining parasitic effects for modern feature sizes. Incorporating parallelism into a simulator at both coarse and fine-grained levels, through the use of message-passing and threading paradigms, is supported by the advent of inexpensive clusters, as well as multi-core technology. However, its effectiveness is reliant upon the development of efficient parallel algorithms for traditional " true SPICE " circuit simulation. In this paper, we will discuss recent advances in fully parallel transistor-level full-chip circuit simulation, concluding with scaling results from a newer strategy for the parallel preconditioned iterative solution of circuit matrices.