A New Efficient FPGA Design of Residue-to-Binary Converter

Abstract

In this paper, we introduce a new 6n bit Dynamic Range Moduli set { 2 2n , 2 2n + 1, 2 2n – 1} and then present its associated novel reverse converters. First, we simplify the Chinese Remainder Theorem in order to obtain an efficient reverse converter which is completely memory less and adder based. Next, we present a low complexity implementation that does not require the explicit use of modulo operation in the conversion process and we demonstrate that theoretically speaking it outperforms state of the art equivalent reverse converters. We also implemented the proposed converter and the best equivalent state of the art reverse converters on Xilinx Spartan 6 FPGA. The experimental results confirmed the theoretical evaluation. The FPGA synthesis results indicate that, on the average, our proposal is about 52.35% and 43.94% better in terms of conversion time and hardware resources respectively.