Automatic RTL Generation Tool of FPGAs for DNNs

Abstract

With the increasing use of multi‐purpose artificial intelligence of things (AIOT) devices, embedded field‐programmable gate arrays (FPGA) represent excellent platforms for deep neural network (DNN) acceleration on edge devices. FPGAs possess the advantages of low latency and high energy efficiency, but the scarcity of FPGA development resources challenges the deployment of DNN‐based edge devices. Register‐transfer level programming, hardware verification, and pre-cise resource allocation are needed to build a high‐performance FPGA accelerator for DNNs. These tasks present a challenge and are time consuming for even experienced hardware developers. There-fore, we propose an automated, collaborative design process employing an automatic design space exploration tool; an automatic DNN engine enables the tool to reshape and parse a DNN model from software to hardware. We also introduce a long short‐term memory (LSTM)‐based model to predict performance and generate a DNN model that suits the developer requirements automati-cally. We demonstrate our design scheme with three FPGAs: a zcu104, a zcu102, and a Cyclone V SoC (system on chip). The results show that our hardware‐based edge accelerator exhibits superior throughput compared with the most advanced edge graphics processing unit.