Coverage of delay faults: When 13% and 99% mean the same

Abstract

A unified classification of delay fault tests that covers all representative types of tests for path and gate delay faults is presented. Timing-related definitions of delay fault testability are transformed into conditions that do not involve circuit delays. These conditions are subsequently used to develop a procedure for fast, simulation-free grading of delay faults. It is shown that, depending on what “detection of a delay fault by an input pattern” means, a randomly generated test sequence can provide very different values of fault coverage; these values range, for one of the examined benchmark circuits, from 13% to over 99%.