Performance gains from partitioning embedded applications in processor-FPGA SoCs

Abstract

In this paper, we propose a hardware/software partitioning method for improving performance in single-chip embedded systems comprised by processor and Field Programmable Gate Array reconfigurable logic. Speedups are achieved by executing critical software parts on the reconfigurable logic. A generic hybrid System-on-Chip platform, which can model existing processor-FPGA systems, is considered. The partitioning flow utilizes an automated analysis procedure at the basic-block level for detecting kernels in software. Three different instances of the considered generic platform and two sets of benchmarks are used in the experiments. For the systems composed by 32-bit processors the speedup of five applications ranges from 1.3 to 3.7 relative to an all software solution. For an 8-bit platform, the speedups of eight DSP algorithms are considerably greater, since they range from 3.2 to 68.4. © Springer-Verlag Berlin Heidelberg 2005.