Multiplier-based double precision floating point divider according to the IEEE-754 standard

Abstract

This paper describes the design and implementation of a unit to calculate the significand of a double precision floating point divider according to the IEEE-754 standard. Instead of the usual digit recurrence techniques, such as SRT-2 and SRT-4, it uses an iterative technique based on the Goldsmith algorithm. As multiplication is the main operation of this algorithm, its implementation is able to take advantage of the efficiency of the embedded multipliers available in the FPGAs. The results obtained indicate that the multiplier-based iterative algorithms can achieve better performance than the alternative digit recurrence algorithms, at the cost of some area overhead. © 2008 Springer-Verlag Berlin Heidelberg.