Multilevel inverter topology with modified pulse width modulation and reduced switch count

Abstract

This paper proposes a new inverter topology with minimum switches, which generates a larger numbers of output voltage levels. The major advantages of the presented topology are minimum number of power switches, minimum cost, reduction in installation area and less switching losses. Different algorithms for determination of the magnitude of voltage sources are presented. Digital based switching scheme has been proposed for low switching frequency operation. Comparative analysis of the proposed inverter topology with earlier presented topologies shows that the performance of the proposed topology is improved as compared with conventional and other recently developed topology. The performance of the presented inverter has been analyzed by simulation, using MATLAB and also the feasibility of the topology has been validated experimentally.