The design technique of using gray code addressing to reduce power dissipation in CPU of pacemaker is presented in this paper. The experimental results of reducing power up to 20% would be a promising result. This work is implemented by using Altera Quartus II 9.0, the device Cylone II EP2C20F484C7 is used. © 2013 IFMBE.
CITATION STYLE
Khoa, L. T., & Trang, H. (2013). Design an optimized CPU architecture for pacemaker applications. In IFMBE Proceedings (Vol. 40 IFMBE, pp. 50–53). https://doi.org/10.1007/978-3-642-32183-2_14
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