Many machine vision applications deal with depth estimation in a scene. Disparity map recovery from a stereo image pair has been extensively studied by the computer vision community. Previous methods are mainly restricted to software based techniques on general-purpose architectures, presenting relatively high execution time due to the computationally complex algorithms involved. In this paper a new hardware module suitable for real-time disparity map computation module is realized. This enables a hardware based occlusion-aware parallel-pipelined design, implemented on a single FPGA device with a typical operating frequency of 511 MHz. It provides accurate disparity map computation at a rate of 768 frames per second, given a stereo image pair with a disparity range of 80 pixels and 640x480 pixel spatial resolution. The proposed method allows a fast disparity map computational module to be built, enabling a suitable module for real-time stereo vision applications. © 2009 Springer Berlin Heidelberg.
CITATION STYLE
Georgoulas, C., & Andreadis, I. (2009). A real-time occlusion aware hardware structure for disparity map computation. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 5716 LNCS, pp. 721–730). https://doi.org/10.1007/978-3-642-04146-4_77
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