RTL Verification and FPGA Implementation of Generalized Neural Networks: A High-Level Synthesis Approach

Abstract

Neural networks (NNs) are used in numerous applications such as audio–video processing and image classification. NNs can address the limitations of the traditional computer algorithms. Recently, the research utilizing field-programmable gate arrays (FPGAs) to implement NNs is on the rise due to low power dissipation, easy and fast reconfigurability offered by these platforms. This is due to the research and development efforts put into the design optimization to improve the throughput of FPGAs. The integration of appropriate hardware with advanced artificial intelligence (AI) software presents many challenges. This paper offers a generalized model of NNs on a FPGA device. In addition, it presents the design process for the high-level synthesis (HLS) tools to implement the project on FPGA. This paper shows the results of latency, timing, pre- and post-synthesis, implementation, and hardware utilization on Xilinx FPGA target device. In this paper, NN for XOR logic gate operation is performed and verified by using HLS tool, and FPGA implementation is proposed. The NN and backpropagation algorithm are developed in high-level programming languages like Python, Java, C, C++. The training part of the NN has been done by using open-source software Dev C++, and tuned weights are taken to Xilinx Vitis HLS. Simulation, synthesis, and implementation are performed by using Xilinx Vitis HLS and Vivado 2020.1 electronic design automation (EDA) tools. NN architecture with tuned weights is implemented on Xilinx ZYNQ FPGA target device. This paper shows that we were able to achieve latency in one clock cycle interval through pipeline and array partition.