Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip

4Citations
Citations of this article
10Readers
Mendeley users who have this article in their library.
Get full text

Abstract

Current compute-intensive applications largely exceed the resources of single-core processors. To face this problem, multi-core processors along with parallel computing techniques have become a solution to increase the computational performance. Likewise, multi-processors are fundamental to support new technologies and new science applications challenges. A specific objective of the Lagarto project developed at the National Polytechnic Institute of Mexico is to generate an ecosystem of high-performance processors for the industry and HPC in Mexico, supporting new technologies and scientific applications. This work presents the first approach of the Lagarto project to the design of multi-core processors and the research challenges to build an infrastructure that allows the flagship core of the Lagarto project to scale to multi- and many-cores. Using the OpenPiton platform with the Ariane RISC-V core, a functional tile has been built, integrating a Lagarto I core with memory coherence that executes atomic instructions, and a NoC that allows scaling the project to many-core versions. This work represents the initial state of the design of mexican multi-and many-cores processors.

Cite

CITATION STYLE

APA

Leyva-Santes, N. I., Pérez, I., Hernández-Calderón, C. A., Vallejo, E., Moretó, M., Beivide, R., … Villa-Vargas, L. A. (2019). Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip. In Communications in Computer and Information Science (Vol. 1151 CCIS, pp. 237–248). Springer. https://doi.org/10.1007/978-3-030-38043-4_20

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free