Creation of vias with optimized profile for 3-D through silicon interconnects (TSV)

Abstract

The continually growing functionality and pattern density of semiconductor devices leads to the development of innovative and cost-effective 3-D stacking and interconnection technologies for ICs and MEMS. These include the formation of vias for interconnects by deep reactive ion etch (DRIE) of silicon. The commonly used DRIE based on a Bosch patent creates holes with vertical sidewalls. However, holes with tapered sidewalls are advantageous, because their widened opening facilitates following deposition and filling processes and a bevelled upper edge of the vias prevents deposited layers from breaking. We created such holes by an optimized positive profile etching (PPE) process. Furthermore, we post-treated holes with vertical sidewalls to eliminate the sharp edge at their opening and to widen this region. We created blind holes with tapered sidewalls with a diameter of 5-10 μm and through silicon holes with a diameter of 40 μm and aspect ratios up to 10. © 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.