Digital circuit vulnerabilities to hardware trojans

Abstract

Integrated Circuits (ICs) are the core of any modern electronic systems, and their security grounds the security of the entire system. Notwithstanding the central impact of ICs security, the horizontal IC design process is extensively practiced as electronic chip, board and system designers nearly always face cost pressures, and tight time-to-market windows. To meet development schedules, they often resort to reuse of their own and/or the third party intellectual property (IP). Using external IPs, however, exposes a design to 3PIPs intentionally modified by inserting a hardware Trojan to tamper with the design and causes its malfunction under very rare circumstances. A hardware Trojan can be realized such that it rarely interferes circuit functionalities at the gate-level and it incurs inconsiderable footprints at the layout-level. This chapter introduces vulnerability analysis flows at the gate- and layout-levels to quantitatively determine susceptibility of a gate-level netlist and a circuit layout’s region to hardware Trojan insertion.