Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging

Abstract

In this research work, an on-board dual-core embedded architecture was developed for SAR imaging systems, implementing a reduced-precision redundancy fault-tolerance mechanism. This architecture protects the execution of the BackProjection Algorithm, capable of generating acceptable SAR images in embedded systems subjected to errors from the space environment. The proposed solution was implemented on a Xilinx SoC device with a dual-core processor. The present work was able to produced images with less 0.65dB on average, than the fault-free image, at the expense of a time overhead upto 33%, when in the presence of error rates similar to the ones measured in space environment. Notwithstanding, the BackProjection algorithm executed upto 1.58 times faster than its single-core version without any fault-tolerance mechanisms.