VHDL design and FPGA implementation of the PWM space vector of an AC machine powered by a voltage inverter

Abstract

This paper presents a VHDL design and FPGA implementation of the space-vector pulse-width modulation (SVPWM) strategy. This design is made in a way that each block of the architecture is described on a separate entity. The global block is represented using the above entities as components. The proposed architecture for SVPWM is composed of four blocks. After the implantation of each block, we note that the resources consumed by the global entity, knowing that the same circuit is used for the different blocks namely the Stratix II device EP2S15F484C3, are 1185 ALUTs. The execution time of our architecture is two clock cycles.