A system generating compacted physical layouts from MOS transistor netlists has been developed. It uses a novel graph-theoretical placement algorithm to maximize diffusion sharing and minimize the wiring area simultaneously. The algorithm is not limited to circuits that have equal numbers of NMOS and PMOS transistors. A special-purpose router using either one-layer or two-layer metal is described. Experimental results for area efficiency and run-time performance are very promising. In conjunction with a well-developed compactor, cells comparable to manual layout can be generated quickly and accurately.
CITATION STYLE
Chen, C. C., & Chow, S. L. (1989). Layout synthesizer: An automatic netlist-to-layout system. In Proceedings - Design Automation Conference (pp. 232–238). Publ by IEEE. https://doi.org/10.1145/74382.74422
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