A new compact multilevel inverter design with less power electronics component

Abstract

Nowadays, multilevel inverter with reduced switch count is more attractive among the researchers due to the unsuitability of the conventional multilevel inverter where the installation space is constrained. Two different algorithms have been proposed for determining the magnitude of DC voltage sources. In this project, a compact version of multilevel inverter design is suggested with reduced and limited power electronic components, which are compared with conventional and recent multilevel inverter topology in terms of a number of levels, auxiliary diode, gate driver circuits, and blocking voltage of switches. Simulation software such as MATLAB/Simulink and laboratory workbench-based experimental test has been conducted. Finally, the comparison between the simulation output and experimental is discussed to prove the superiority of suggested topology.