Thermal design of multi-fin Ga2O3 vertical transistors

Abstract

Ultra-wide bandgap β-gallium oxide (Ga2O3) vertical device technologies are of significant interest in the context of the development of next-generation kV-range power switching devices. In this work, thermal analysis of vertical fin channel-based metal-oxide-semiconductor field-effect transistors (or fin field-effect transistors—FinFETs) was performed using infrared thermal microscopy and coupled electro-thermal modeling. FinFETs with different fin width and channel spacing were characterized to study the thermal design trade-off when attempting to minimize the footprint of multi-fin FinFET arrays. A 50 × 50 μm2 scaled FinFET cell array exhibited an ∼23× higher temperature rise as compared to a 5-fin device. Devices with different orientations were fabricated and characterized. By rotating the fin channel aligned along the [010] direction by 90º, the channel temperature rise reduced by 30%, due to the anisotropy of the Ga2O3 thermal conductivity (κ). Electro-thermal modeling shows that a 20% reduction in the temperature rise is possible by fabricating devices on a (010)-oriented substrate as compared to the tested devices built on a (001) substrate. These results indicate the importance of the electro-thermal co-design process for Ga2O3 vertical FinFET cell arrays.