Abstract
Recent years have seen a new generation of HLS tools, which do not only allow to generate hardware architectures from hardware behavioral models, but perform synthesis starting from algorithms specified in HLLs. One of the reasons for this development is the ever growing popularity of reconfigurable logic, which aims at providing the performance and energy efficiency of integrated circuits at a flexibility that is very close to software.
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CITATION STYLE
Schmid, M., Schmitt, C., Hannig, F., Malazgirt, G. A., Sonmez, N., Yurdakul, A., & Cristal, A. (2016). Big data and HPC acceleration with Vivado HLS. In FPGAs for Software Programmers (pp. 115–136). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_7
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