Analyzing circuit layout to probing attack

Abstract

Probing attacks against Integrated Circuits (IC) for security critical applications have become a serious concern. With the help of modern IC debug technologies, an attacker could remove layers of materials and expose wires carrying security critical information for probing. Existing protection methods use active shields to detect such attacks. However, problems such as ineffective top layer wire mesh and reused hardware Intellectual Property (IP) blocks exist, which threatens active shield security. Moreover, protection for mass-produced products such as smartcards and security tokens has been overlooked, partly due to they can neither afford the area cost or technology requirements of state-of-the-art protection designs. In this chapter, we cover known techniques in performing probing attacks, the problem of protection against probing attacks, and present a layout-driven framework to assess designs for vulnerabilities to probing attacks.