Stress engineering for drive current enhancement in silicon carbide (sic) power mosfets

Abstract

The poor interface quality of the Silicon Carbide/oxide (SiC/SiO2) interface severely degrades the electron surface channel mobility in SiC-based power devices. Based on transfer characteristic simulations (with a deck calibrated to experimental data), this work predicts improved mobility with stress engineering, a well-established technique for performance enhancement in low power silicon (Si) transistor technology. Process simulation of Si and SiC-based devices with Silicon Nitride (Si3N4) stressor layer has been carried out to estimate the stress generated in the channel. SiC D-MOSFET we have also computed the effect of varying stress magnitude, direction, and position in the device.