Six networks on a universal neuromorphic computing substrate

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Abstract

In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart of this system lies a mixed-signal chip, with analog implementations of neurons and synapses and digital transmission of action potentials. Major advantages of this emulation device, which has been explicitly designed as a universal neural network emulator, are its inherent parallelism and high acceleration factor compared to conventional computers. Its configurability allows the realization of almost arbitrary network topologies and the use of widely varied neuronal and synaptic parameters. Fixed-pattern noise inherent to analog circuitry is reduced by calibration routines. An integrated development environment allows neuroscientists to operate the device without any prior knowledge of neuromorphic circuit design. As a showcase for the capabilities of the system, we describe the successful emulation of six different neural networks which cover a broad spectrum of both structure and functionality. © 2013 Pfeil, Grübl, Jeltsch, Müller, Müller, Petrovici, Schmuker, Brüderle, Schemmel and Meier.

Figures

  • FIGURE 1 | Microphotograph of the Spikey chip (fabricated in a 180-nm CMOS process with die size 5 mm × 5 mm). Each of its 384 neurons can be arbitrarily connected to any other neuron. In the following, we give a short overview of the technical implementation of neural networks on the Spikey chip. (A) Within the synapse array 256 synapse line drivers convert incoming digital spikes (blue) into a linear voltage ramp (red) with a falling slew rate t fall. For simplicity, the slew rate of the rising edge is not illustrated here, because it is chosen very small for all emulations in this study. Each of these synapse line drivers are individually driven by either another on-chip neuron (int), e.g., the one depicted in (C), or an external spike source (ext). (B) Within the
  • FIGURE 2 | Integrated development environment. User access to the Spikey chip is provided using the PyNN neural network modeling language. The control software controls and interacts with the network module which is operating the Spikey chip. The RAM size (512 MB) limits the total number of spikes for stimulus and spike recordings to approximately 2·108 spikes. The required data for a full configuration of the Spikey chip has a size of approximately 100 kB.
  • Table 1 | List of analog current and voltage parameters as well as digital configuration bits.
  • FIGURE 3 | Calibration results for membrane time constants. Before calibration (left), the distribution of τm values has a median of τ̃m = 15.1 ms with 20th and 80th percentiles of τ 20m = 10.3 ms and τ 80 m = 22.1 ms, respectively. After calibration (right), the distribution median lies closer to the target value and narrows significantly: τ̃m = 11.2 ms with τ 20m = 10.6 ms and τ 80m = 12.0 ms. Two neurons were discarded, because the automated calibration algorithm did not converge.
  • FIGURE 4 | (A) Synfire chain with feedforward inhibition. The background is only utilized in the original model, where it is implemented as random Gaussian current. For the presented hardware implementation it has been omitted due to network size constraints. As compensation for missing background stimuli, the resting potential was increased to ensure a comparable excitability of the neurons. (B) Hardware emulation. Top: raster plot of pulse packet propagation 1000 ms after initial stimulus. Spikes from RS groups are shown in red and spikes from FS groups are denoted by blue color and background. Bottom: membrane potential of the first neuron in the fourth RS group, which is denoted by a dashed horizontal line. The cycle duration is
  • FIGURE 5 | (A) Network topology of a balanced random network. Populations consisting of Ne =100 excitatory and N i =25 inhibitory neurons (gray circles), respectively, are stimulated by populations of Poisson sources (black circles). We use Np =100 independent sources for excitation and Nq = 25 for inhibition. Arrows denote projections between these populations with connection probabilities p= 0.1, with solid lines for excitatory and dotted lines for inhibitory connections. Dot and dash lines are indicating excitatory projections with short-term depression. (B) Top: raster plot of a software simulation. Populations of excitatory and inhibitory neurons are depicted with white and gray background,
  • FIGURE 6 | (A) Topology of a soft winner-take-all network with 50 excitatory (gray circles) and 16 inhibitory neurons. Solid and dotted arrows denote excitatory and inhibitory connections, respectively. The strength profile of recurrent connections between excitatory neurons and external stimulations is schematized in blue and red, respectively (for details, see text). All projections between neuron populations have a connection probabilities of p=1, except the projection between the excitatory and inhibitory neuron population (p=0.6). (B) Results of software simulation (SW). Black curve: total firing rate of the reference half where constant external stimulation is received (r 1 =50 Hz at µext =neuron index 13). Gray curve: total firing rate of the neurons in the half of the ring where varying external stimulation with rate r 2 between zero and 100 Hz is received (at
  • FIGURE 7 | (A) Schematic of the cortical layer 2/3 attractor memory network. Two hypercolumns, each containing two minicolumns, are shown. For better readability, only connections that are active within an active pattern are depicted. See text for details. (B) Software simulation of spiking activity in the cortical attractor network model scaled down to 192 neurons (only pyramidal and RSNP cells shown, basket cells spike almost continuously). Minicolumns belonging to the same pattern are grouped together. The broad stripes of activity are generated by pyramidal cells in active attractors. The interlaced narrow stripes of activity represent pairs of RSNP cells, which spike when their home minicolumn is inhibited by other active patterns. (C) Same as (B), but on hardware. The raster plot is noisier and the duration of attractors (dwell time) are less stable than in software due to fixed-pattern noise on neuron and synapse circuits. For better

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Pfeil, T., Grübl, A., Jeltsch, S., Müller, E., Müller, P., Petrovici, M. A., … Meier, K. (2013). Six networks on a universal neuromorphic computing substrate. Frontiers in Neuroscience, (7 FEB). https://doi.org/10.3389/fnins.2013.00011

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