Compiler efficient and power aware instruction level parallelism for multicore architecture

Abstract

The paradigm shift to multicore processors for better performance has added a new dimension for research in compiler driven instruction level parallelism. The work in this paper proposes an algorithm to group dependent instructions of a basic block of control flow graph into disjoint sub-blocks during the SSA form translation. Following this an algorithm is presented which constructs a graph tracking dependencies among the sub-blocks spread all over the program. A global scheduler of the compiler is presented which selectively maps sub-blocks in the dependency graph on to multiple cores, taking care of the dependencies among them. The proposed approach conforms to spatial locality, aims for minimized cache coherence problems, communication latency among the cores and overhead of hardware level instruction re-ordering while extracting parallelism and saving power. The results observed are indicative of better and balanced speedup per watt consumed. © 2012 Springer-Verlag.