FORCING OF TRANSISTOR STACKS

Abstract

The transistor stack is a leakage reduction technique which works both in active and stand-by mode. It is based on the observation that two off-state transistors connected in series cause significantly less leakage than a single device. The leakage current of the stack is even smaller than the leakage of a single device with double channel length. Corresponding to eq. 1.5, doubling the channel length reduces the off-current by a factor of two. However, in modern deep sub-micron devices the threshold voltage may decrease for longer channels due to the reverse short channel effect. Therefore, leakage reduction is less effective. Fig. 4.1 shows a schematic of an NMOS transistor stack. The threshold voltage is modeled linearly by