Abstract
The design of a new configurable hybrid current-mode/static CBL-CMOS cell is presented. This cell can be used in order to obtain the optimum partitioning between conventional and low-noise logic in the digital part of a mixed-signal circuit, resulting in a optimum power/noise solution. This new cell has been compared with the original logic families obtaining acceptable results with low hardware cost. A combinational multiplier has been designed as a demonstrator example of the utility of the proposed cells. © Springer-Verlag Berlin Heidelberg 2003.
Cite
CITATION STYLE
Jiménez, R., Parra, P., Sanmartín, P., & Acosta, A. J. (2003). A new hybrid CBL-CMOS cell for optimum noise/power application. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2799, 491–500. https://doi.org/10.1007/978-3-540-39762-5_55
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