This chapter presents a set of built-in operators that will allow basic logic expressions to be modeled within a Verilog module. This chapter then presents a series of combinational logic model examples.
CITATION STYLE
LaMeres, B. J. (2019). Modeling Concurrent Functionality in Verilog. In Quick Start Guide to Verilog (pp. 23–49). Springer International Publishing. https://doi.org/10.1007/978-3-030-10552-5_3
Mendeley helps you to discover research relevant for your work.