We propose a junctionless tunnel FET architecture with a heterostructure at the source/channel interface. We show that the use of a low bandgap material in the source of this device results in significant ON current improvement. We further show that ON current improvement can also be achieved by using a low-k isolation dielectric. The proposed device architecture which combines the merits of both junctionless FETs and Tunnel FETs can be a potential candidate for sub-20nm technology node.
CITATION STYLE
Gundapaneni, S., Konar, A., Bajaj, M., & Murali, K. V. R. M. (2014). Improved Performance of Junctionless Tunnel FETs with Source/Channel Heterostructure. In Environmental Science and Engineering (pp. 219–290). Springer Science and Business Media Deutschland GmbH. https://doi.org/10.1007/978-3-319-03002-9_73
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