Structured design approach for an optimal programmable synchronous security processor

Abstract

A new security processor has been recently proposed which accepts the assembly code for arbitrary security algorithms, and executes it efficiently, thanks to its use of a data-flow architecture that distributes arithmetic and logical Function Units (FUs) over a number of Execution Regions (ERs). In this paper, a structured approach is presented to determine the optimal solution of the processor architecture in which one seeks the best combination of the number of ERs and the assignment of 27 FUs to these ERs. In order to cover the huge design space, a structured approach has been adopted which is based on the use of a powerful software simulator and the customization of the Genetic Algorithm NSGA-II for efficient optimization. Numerical results have been obtained and the optimal security processor architecture has been deduced by considering the AES Encryption algorithm as the reference assembly code.