A Low-Power Embedded IoT Microprocessor Design and Validation

Abstract

In this paper, the four proposed low-power design techniques are used to design an ARM-lite Internet-of-Thing (IoT) embedded microprocessor. The four techniques are gated-clock, memory-interleaving, structure-reordering, and instruction-coding. These four mechanisms are implemented within this microprocessor, and then Xilinx FPGA is used to validate whether the design is functionally correct. Here, the gate-level low-power design techniques are focused for IoT embedded microprocessors; it can be found that the proposed low-power schemes are application program dependent. From our experimental results, after applying the four techniques, there was an average of 18% less power consumption and without delay time penalty than the original design. The gated-clock and memory-interleaving techniques achieved better power-saving effectiveness than the other techniques. The proposed gate-level low-power schemes are also suitable for other special purpose microprocessors. From experimental results, for specific-application IoT microprocessor, there is better power-saving to incorporate more detailed software analysis. However, for the general-application IoT microprocessor, the future circuit-level low-power techniques need to be included for more effective power-saving.