Time-domain weighted-sum calculation for ultimately low power VLSI neural networks

Abstract

Time-domain weighted-sum operation based on a spiking neuron model is discussed and evaluated from a VLSI implementation point of view. This calculation model is useful for extremely low-power operation because transition states in resistance and capacitance (RC) circuits can be used. Weighted summation is achieved with energy dissipation on the order of 1 fJ using the current CMOS VLSI technology if 1 GΩ order resistance can be used, where the number of inputs can be more than a hundred. This amount of energy is several orders of magnitude lower than that in conventional digital processors. In this paper, we show the software simulation results that verify the proposed calculation method for a 500-input neuron in a three-layer perceptron for digit character recognition.