Instruction Set Extensions for Cryptographic Applications

Abstract

9.1 Introduction Instruction-set extension (ISE) has been widely studied as a means toimprove the performance of microprocessor devices running cryptographic applications. It consists, essentially, in endowing an existing processor with a set of additional in-structions that can be useful for speeding up specific cryptographic computations. Recently, researchers became aware of the following: " The efficiency of an imple-mentation algorithm often depends heavily on the details of the target platform, e.g., on the instruction set or the pipeline of a processor. Hence, theoretical complexity measures, such as the bit complexity, can be misleading in practice " ([47]). In this chapter, we will analyze the implications of designing and deploying an ISE for a microprocessor. We will give details on existing research proposals for various cryptographic applications, highlighting the associated benefits and limita-tions, and we will show the ISEs that are available in some market products and are proposed in research studies. 9.1.1 Instruction Set Architecture Instruction-set extension can be better understood only after having a clear idea of what an instruction-set is. At the higher level, an instruction-set (or instruction-set architecture – ISA) can be defined as the pool of instructions made available by a processor to the assembler programmer, or to the compiler. In this sense, the ISA defines a significant quote of the programming interface of the processor: the basic operations that the outside world can ask the processor to do. The whole programming interface of a processor is surely wider than the sole ISA and, in brief, it encompasses also the structure and features of the processor