Large Scale Optoelectronic Integration of Asynchronous Analog Neural Networks

Abstract

A simple circuit architecture in standard CMOS technology for the optoelec-tronic implementation of analog continuous-time neural networks (NN) is presented. The circuit enables the implementation of recurrent NN models with analog synapses and neurons, with continuous dynamics. The basic cell consists of a synapse coupled with a distributed neuron, where synaptic linear superposition and neuron nonlinear thresholding are combined together, using only five MOS transistors and one phototransistor per synapse. The synaptic interaction matrix is imaged continuously on the chip from a spatial light modulator, thus allowing fast reprogramming of the connections. The performance of the proposed system is illustrated by some measurements of synapse and neuron characteristics on a 16 neuron (256 synapse) prototype fabricated in MOSIS CMOS technology. The expected performance and limitations of a scaled up system are discussed. Careful examination of existing analog NN hardware reveals a tradeoff between the complexity of the implemented model and the size of the implemented network [1]. We henceforth present an optoelectronic NN implementation with fully analog neurons and synapses, using one phototransistor and five MOS transistors per synapse. The underlying principle is to image the synaptic interaction matrix from a spatial light modulator onto a Vl.SI circuit which performs the dynamics of the NN. Similar implementations were demonstrated earlier for binary neurons and analog synapses [2,3]. The system described here extends the previous implementations to analog neurons. The general asynchronous analog NN model we seek to implement satisfies [4]: d (r·-+ 1) u ·=I·+"" T.· ·V.